This disclosure is related to memory devices that may be employed within computing platforms.
Computing platforms may include one or more dynamic random access memory (DRAM) devices. DRAM devices may be used in a variety of applications, including main system memory and/or graphics memory, to list a couple of examples. For some computing platforms, one or more DRAM devices may be coupled to a graphics processing unit (GPU). The GPU may be located on a motherboard for some platforms, and for other platforms the GPU may be located on an adapter card.
A DRAM device comprises volatile memory, and accordingly, a device charge must periodically be refreshed. For example, memory bank charge of a DRAM device may be refreshed in approximately 64 ms or less, in accordance with Joint Electron Device Engineering Council (JEDEC) standards. A DRAM device may employ integrated refresh and timing logic to perform refresh functions, and/or may employ refresh and timing logic of a computing platform to perform refresh functions, for example. Typically, DRAM devices may employ a power management mode such as a self-refresh mode. A self-refresh mode may be enabled when a DRAM device is not actively being used, for example. In a self-refresh mode, DRAM charge is periodically refreshed by employing integrated DRAM refresh logic. DRAM devices may periodically enter and exit modes such as self-refresh mode. Typically, delays may be incurred when exiting modes such as a self-refresh mode, due at least in part, to a time delay that may be incurred to synchronize or relock the DRAM device with a computing platform clock, for example.